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| 1EDI2002AS_15 Datasheet, PDF (101/147 Pages) Infineon Technologies AG – Single Channel Isolated Driver for Inverter Systems AD Step | |||
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EiceDRIVER⢠SIL
1EDI2002AS
Register Description
Primary Clock Supervision Register
This register shows the result of the Primary Clock Supervision function.
PCS
Primary Clock Supervision Register
Offset
0BH
Wakeup Value
n.a.
Reset Value
0001H
15
8
CS1
rh
7
2
1
0
0
LMI
P
r
rh
rh
Field
CS1
0
LMI
P
Bits
Type Description
15:8
rh
Primary Clock Supervision
This bit field is written by hardware by the Primary Clock
Supervision function and gives the number of measured
OSC1 clock cycles.
Note: This bit field can be cleared by setting bit
PCTRL.CLRP.
7:2
r
Reserved
Read as 0B.
1
rh
Last Message Invalid Notification
This bit indicates if the last received SPI Message was
correctly processed by the device.
0B: Previous Message was processed correctly.
1B: Previous Message was discarded.
0
rh
Parity Bit
Odd Parity Bit.
Datasheet
101
Hardware Description
Rev. 3.1, 2015-07-30
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