1EDI2002AS_15 Datasheet, PDF (65/147 Pages) Infineon Technologies AG – Single Channel Isolated Driver for Inverter Systems AD Step

EiceDRIVER™ SIL
1EDI2002AS
Protection and Diagnostics
3.2.4 Output Stage Monitoring
The Output Stage Monitoring functionality is summarized in Table 3-5:
Table 3-5 Output Stage Monitoring Overview
Parameter
Short Description
Function
Monitoring of signals TON and TOFF.
Periodicity
Continuous.
Action in case of failure event ^{1. Tristate Output Stage (bit SSTAT.HZ set)}
2. Bit SCTRL.OSTC and error Flag SER.OSTER are set.
3. Assertion of signal NFLTA.
Programmability
Yes (can be disabled).
In-System Testability
Yes.
Signals TON and TOFF are normally connected to an external booster (Figure 5-1). In case the inputs of the
booster can not be driven (e.g. short circuit), the resulting high currents may lead to the destruction of the
1EDI2002AS and / or of the booster. This failure case is avoided thanks to the Output Stage Monitoring function.
When levels at TON and TOFF differ from the expected levels, the output stage is tristated and bit SSTAT.HZ is
set. A transition of bit SSTAT.HZ from 0_B to 1_B generates an Event Class A: bit SCTRL.OSTC and error flag
SER.OSTER are set, signal NFLTA is asserted (see Chapter 2.4.7).
The monitoring is continuous, but is inhibited for the inhibition time t_OSM after commutation. At turn-on, time t_OSM is
counted from the beginning of the turn-on sequence. At turn-off, time t_OSM is counted from the moment where the
hard switching action takes place (after the TTOFF plateau). Signal TON is compared against V_OSMON. Signal
TOFF is compared against V_OSMOF.
Note: Bit SCTRL.OSTC is cleared either by setting bit PCTRL.CLRS or by a falling edge of signal OSD.
In OPM5 and OPM6, Output Stage Monitoring for TON is disabled.
Output Stage Monitoring is disabled when the device is already in tristate (for example, when pin OSD is at High
Level). The Output Stage returns from tristate to normal conditions when bit SSTAT.HZ is cleared. Clearing bit
SSTAT.HZ reactivates the OSM (after the duration of the blanking time).
Note: The OSM can be permanently disabled by setting bit SCFG.OSMD, for both TON and TOFF.
The OSM can be tested on system level by (for example) pulling the IGBT gate signal high while the device issues
a PWM Low command. This can be done for example in combination with the ASC function of Infineon’s
1EBN100XAE “EiceDRIVER™ Boost” booster stage. It can then be verified that the reaction of the device
corresponds to the expected behavior.
Datasheet
65
Hardware Description
Rev. 3.1, 2015-07-30