1EDI2002AS_15 Datasheet, PDF(53/147 Page) Infineon Technologies AG – Single Channel Isolated Driver for Inverter Systems AD Step

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1EDI2002AS_15 Datasheet, PDF (53/147 Pages) Infineon Technologies AG – Single Channel Isolated Driver for Inverter Systems AD Step

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EiceDRIVERâ¢ SIL

1EDI2002AS

Functional Description

2.4.10.1.4 Configuration of the EN/FEN Mode

The mode of operation of pin EN/FEN can be programmed by writing bit field PCFG2.FEN. The description of the

operating modes is given in Chapter 2.4.8.

Note: Register PCFG2 can only be written if bit PCFG.CFG1 is set.

2.4.10.1.5 Configuration of the Digital Channel

The direction of pin DIO1 can be programmed by writing bit field PCFG2.DIO1. The direction of pin DIO2 can be

programmed by writing bit field SCFG2.DIO2.

Note: Register PCFG2 can only be written if bit PCFG.CFG1 is set. Register SCFG2 can only be written if bit

SCFG.CFG2 is set.

2.4.10.1.6 Configuration of DOUT Signal Activation

The signal at pin DOUT can be activated or deactivated by programming bit PCFG2.DOEN1. If deactivated, pin

DOUT delivers a steady Low signal. The rest of the logic is not affected by this setting. Besides, bit SCFG2.ISMEN

has to be set as well. Furthermore, permanent DESAT clamping shall be deactivated (SCFG.DSTCEN cleared).

Note: Register PCFG2 can only be written if bit PCFG.CFG1 is set. Register SCFG2 can only be written if bit

SCFG.CFG2 is set

2.4.10.1.7 Configuration of the VBE Compensation

The VBE compensation of signal TON and TOFF can be activated or deactivated by writing bit SCFG.VBEC. See

Chapter 2.4.6 for more details.

2.4.10.1.8 Deactivation of Output Stage Monitoring

The OSM function can be disabled by setting bit SCFG.OSMD.

2.4.10.1.9 Deactivation of Events Class A due to pin OSD

By setting bit SCFG.OSDAD, Event Class A are not issued in case of a Tristate event generated by pin OSD. Other

actions such as tristating the output stage or setting bit SER.OSTER are performed normally.

2.4.10.1.10 Clamping of DESAT pin

By setting bit SCFG.DSTCEN, the DESAT signal is clamped to VGND2 while the output stage of the device issues

a PWM OFF command and during blanking time periods. By clearing bit SCFG.DSTCEN, the DESAT clamping is

only activated during blanking time periods.

In order to use the IGBT Monitoring function, bit SCFG.DSTCEN shall be cleared.

Datasheet

Hardware Description

Rev. 3.1, 2015-07-30

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