1EDI2002AS_15 Datasheet, PDF (54/147 Pages) Infineon Technologies AG – Single Channel Isolated Driver for Inverter Systems AD Step

EiceDRIVER™ SIL
1EDI2002AS
Functional Description
2.4.10.1.11 Activation of the Pulse Suppressor
The pulse suppressor function associated with the TTOFF function can be activated by setting bit SCFG.PSEN.
When activated, SRTTOF.RTVAL shall be programmed with a minimum value (see Page 119).
2.4.10.1.12 Configuration of the Verification Mode Time Out Duration
The duration of the time out in verification mode is selectable via bit SCFG.TOSEN.
2.4.10.1.13 DESAT Threshold Level Configuration
By writing bit field SCFG2.DSATL, it is possible to select the detection level of the DESAT comparator (which is
also the level for the DOUT function).
Note: Register SCFG2 can only be written if bit SCFG.CFG2 is set.
2.4.10.1.14 Configuration of the TTON Delay
The TTON delay can be configured by writing bit field SCFG2.TTOND. Programming 0_H as a delay value disables
the TTON for all turn-on sequences. Hard turn-on are performed instead. In case the TTON function is wished, a
minimum value for the delay has to be programmed (see Page 112).
The TTON delay can be calibrated using the TCF feature of the device.
Note: Register SCFG2 can only be written if bit SCFG.CFG2 is set.
2.4.10.1.15 Configuration of DACLP Activation Mode
The DACLP activation mode can be programmed by writing bit SCFG2.ACLPM. When this bit is cleared, signal
DACLP is deactivated at every Turn-Off sequence (with the programmed activation time). When it is set, DACLP
is deactivated only in case of an Emergency Turn-Off sequence.
Note: Register SCFG2 can only be written if bit SCFG.CFG2 is set.
2.4.10.1.16 OVLO3 Operation Mode
The activation mode of the OVLO3 function can be selected by programming bit SCFG2.OVLO3D. When this bit
is cleared, an Event Class B is generated in case on a OVLO3 event (V_EE2 above a given threshold). When this
bit is set, no Event Class B is generated in case of an OVLO3 event, but an Event Class C: the OPM mode is not
affected, the output stage is not turned off and signal NFLTB is not activated. Nevertheless, bit SER.OVLO3ER is
set (and mirrored to PER.OVLO3ER).
Note: Register SCFG2 can only be written if bit SCFG.CFG2 is set.
2.4.10.1.17 Configuration of the TTOFF Delays
The TTOFF delays for Regular and Safe Turn-Off sequences can be programmed separately by writing registers
SRTTOF or SSTTOF. The delay for Regular Turn-Off can also be configured using the Timing Calibration Feature.
Datasheet
54
Hardware Description
Rev. 3.1, 2015-07-30