1EDI2002AS_15 Datasheet, PDF (91/147 Pages) Infineon Technologies AG – Single Channel Isolated Driver for Inverter Systems AD Step

EiceDRIVER™ SIL
1EDI2002AS
Register Description
Primary Configuration Register
This register is used to select the configuration of the device.
PCFG
Primary Configuration Register
Offset
04_H
Wakeup Value
n.a.
Reset Value
0004_H
15
8
0
r
7
6
5
4
3
2
1
0
0
OSMAEN OSTAEN
CFG1
PAREN
LMI
P
r
rw
rw
rwh
rw
rh
rh
Field
0
OSMAEN
OSTAEN
CFG1
PAREN
LMI
P
Bits
Type Description
15:6
r
Reserved
Read as 0_B.
5
rw
NFLTA Activation on OSM Event Enable Bit
This bit enables the activation of signal NFLTA in case of
a transition from 0_B to 1_B of bit PSTAT2.OSTC.
0_B: NFLTA activation is disabled.
1_B: NFLTA activation is enabled
4
rw
NFLTA Activation on Tristate Event Enable Bit
This bit enables the activation of signal NFLTA in case of
a transition from 0_B to 1_B of bit PER.OSTER.
0_B: NFLTA activation is disabled.
1_B: NFLTA activation is enabled
3
rwh
Advanced Primary Configuration Enable Bit
This bit enables write accesses to register PCFG2.
0_B: Write access to PCFG2 are discarded.
1_B: Write access to PCFG2 are executed normally.
This bit is automatically cleared when mode OPM2 is left.
2
rw
Parity Enable Bit
This bit indicates if the SPI parity error detection is active
(reception only).
0_B: Parity Check is disabled.
1_B: Parity Check is enabled.
1
rh
Last Message Invalid Notification
This bit indicates if the last received SPI Message was
correctly processed by the device.
0_B: Previous Message was processed correctly.
1_B: Previous Message was discarded.
0
rh
Parity Bit
Odd Parity Bit.
Datasheet
91
Hardware Description
Rev. 3.1, 2015-07-30