1EDI2002AS_15 Datasheet, PDF (51/147 Pages) Infineon Technologies AG – Single Channel Isolated Driver for Inverter Systems AD Step

EiceDRIVER™ SIL
1EDI2002AS
Functional Description
Table 2-13 Reset Events Summary
Reset Event
Primary
Secondary
UVLO2 Event
-
Hard Reset
OSC2 not starting -
at power-up
OSC2 misfunction -
during operation
Hard Reset
Soft Reset
IREF2 open
-
VREG shorted to -
ground
Memory Error on -
Secondary
Hard Reset
Undefined
Hard Reset
Notification
(primary)
Notification
(secondary)
• Event Class B (NFLTB • Signal NUV2 at Low level
activated, bit PER.CER1
(if V_CC2 <V_UVLO2).
set).
• Bit SER.RST2 (once V_CC2
• Bit PSTAT.SRDY cleared valid again).
for the duration of the
• Output Stage issues a
failure.
PWM OFF command.
• OSD pin functionality
operational for: V_CC2 >
V_RST2.
• Event Class B
• Output Stage issues a
(NFLTB activated, bit
PWM OFF command.
PER.CER1 set)
• OSD pin functionality
• Bit PSTAT.SRDY cleared operational.
• Event Class B
• Output Stage issues a
(NFLTB activated, bit
PWM OFF command.
PER.CER1 set)
• OSD pin functionality
• Bit PSTAT.SRDY cleared operational.
for the duration of the
failure.
• Event Class B
None.
(NFLTB activated, bit
PER.CER1 not)
• Bit PSTAT.SRDY cleared
• Event Class B
• Signal NUV2 at Low
(NFLTB activated, bit
Level.
PER.CER1 set)
• Output Stage issues a
• Bit PSTAT.SRDY cleared. PWM OFF command.
• Event Class B
• Output Stage issues a
(NFLTB activated, bit
PWM OFF command.
PER.CER1 set).
• OSD pin functionality
• Bit PSTAT.SRDY cleared. operational.
All reset events set the device in Mode OPM0. In a soft reset, the logic works further, but the registers use the
default values.
In case of a reset condition on the primary side, the behavior of the pin of the device is defined in Table 2-14.
Table 2-14 Pin behavior (primary side) in case of reset condition
Pin
Output Level Comments
SDO
Low
DOUT
Tristate
NFLTB
Low
NFLTA
High
NRST/RDY
Low (GND1)
Datasheet
51
Hardware Description
Rev. 3.1, 2015-07-30