1EDI2002AS_15 Datasheet, PDF (68/147 Pages) Infineon Technologies AG – Single Channel Isolated Driver for Inverter Systems AD Step

• Memory error (both primary and secondary).
EiceDRIVER™ SIL
1EDI2002AS
Protection and Diagnostics
3.3.2.1 Lifesign watchdog
The primary and the secondary chips monitor each other by the mean of a lifesign signal. The periodicity of the
lifesign is typically t_LS. Each chip expects a lifesign from its counterpart within a given time window. In case two
consecutive lifesign errors are detected by a chip, an Event Class B is generated. Depending on which side has
detected the error, either bit PER.CER1 or SER.CER2 is set.
Note: Bits PER.CER1 and SER.CER2 indicate a loss of communication event. The current status of the internal
communication is indicated by bit PSTAT.SRDY.
3.3.2.2 Oscillator Monitoring
The main oscillators on the primary and on the secondary side are monitored continuously. Two distinct
mechanisms are used for this purpose:
• Lifesign Watchdog allows to detect significant deviations from the nominal frequency (both primary and
secondary, see above).
• Open / short detection on pin IREF1.
• Open detection on pin IREF2.
In case a failure is detected on pin IREF1, the primary chip is kept in reset state for the duration of the failure and
signal NRST/RDY is asserted, This leads to the detection of a lifesign error by the secondary chip, generating thus
an Event Class B.
In case a failure is detected on pin IREF2, an Emergency (regular) Turn-Off sequence is initiated. The secondary
chip is kept in reset state for the duration of the failure. This leads to the detection of a lifesign error by the primary
chip, generating thus an Event Class B.
3.3.2.3 Memory Supervision
The configuration parameters of the device, stored in the registers, are protected with a parity bit protection
mechanism. Both primary and secondary chips are protected (refer to Chapter 4).
In case a failure is detected on the primary chip, it is kept in reset state, and both signal NRST/RDY and NFLTB
are asserted. The secondary side initiates an Emergency (Regular) Turn-Off sequence.
In case a memory failure is detected by the secondary chip, an Emergency (Regular) Turn-Off sequence is
initiated. The secondary chip is kept in reset state for the duration of the failure. This leads to the detection of a
lifesign error by the primary chip, generating thus an Event Class B.
Datasheet
68
Hardware Description
Rev. 3.1, 2015-07-30