1EDI2002AS_15 Datasheet, PDF (52/147 Pages) Infineon Technologies AG – Single Channel Isolated Driver for Inverter Systems AD Step

EiceDRIVER™ SIL
1EDI2002AS
Functional Description
In case of a hard reset condition on the secondary side, the behavior of the pin of the device is defined in
Table 2-15.
Table 2-15 Pin behavior (secondary side) in case of reset condition
Pin
Output Level Comments
TON
TOFF
DESAT
Low (V_EE2)
Low (V_EE2)
Low (GND2)
Passive Clamping
Passive Clamping
Clamped.
GATE
DACLP
Low (V_EE2)
High (5V)
Passive Clamping
Active clamping disabled by default.
NUV2
Low (GND2)
2.4.10 Operation in Configuration Mode
This section describes the mechanisms to configure the device.
2.4.10.1 Static Configuration Parameters
Static parameters can configured when the device is in Mode OPM2 by writing the appropriate register.
Once Mode OPM2 is left with the SPI Command EXIT_CMODE, the configuration parameters are frozen on both
primary and secondary chips. This means in particular that write accesses to the corresponding registers are
invalidated. This prevents static configurations to be modified during runtime. Besides, the configuration
parameters on the primaryand secondary side are protected with a memory protection mechanism. In case the
values are not consistent, a Reset Event and / or an Event Class B is generated.
2.4.10.1.1 Configuration of the SPI Parity Check
The SPI interface supports by default an odd parity check. The Parity Check mechanism (active at the reception
of an SPI word) can be disabled by setting bit PCFG.PAREN to 0_B. Setting bit PAREN to 1_B enables the Parity
Check.
Parity Bit Generation for the transmitter can not be disabled.
2.4.10.1.2 Configuration of NFLTA Activation in case of Tristate Event
Signal NFLTA is normally activated by a state transition of the internal state machine. However, it can be also
configured to be activated in relation with the primary bits PER.OSTER or PSTAT2.OSTC. This is configured
thanks to bits PCFG.OSTAEN and PCFG.OSMAEN.
2.4.10.1.3 Configuration of the STP Minimum Dead Time
The minimum dead time for the Shoot-Through Protection can be programmed by writing bit field
PCFG2.STPDEL. The value programmed corresponds to a number of OSC1 clock cycles.
Note: Register PCFG2 can only be written if bit PCFG.CFG1 is set.
Datasheet
52
Hardware Description
Rev. 3.1, 2015-07-30