HYE18P32160AC Datasheet, PDF (52/53 Pages) Infineon Technologies AG – 32M Synchronous Burst CellularRAM

HYE18P32160AC(-/L)9.6/12.5/15
32M Synchronous Burst CellularRAM
Appendix B: S/W Register Entry Mode (“4-cycle method”)
D15
D8 D7 D6 D5 D4 D3 D2 D1 D0 _DQ<15:0>
0
0 PM TCSR DPD* 0
PASR
Control Register
Page Mode Bit
D7
page mode
0 disabled (def.)
1
enabled
Deep Power Down Mode
D4
power down
X disabled (def.)
D15....D8, D3:
reserved, must be set to '0'.
Temperature-Compensated
Self-Refresh
D6 D5 max. case temp.
11
+85°C (def.)
00
+70°C
01
+45°C
10
+15°C
Partial Array Self Refresh
D2 D1 D0 refreshed memory area
0 0 0 entire memory array (def.)
0 0 1 lower 1/2 of memory array
0 1 0 lower 1/4 of memory array
0 1 1 lower 1/8 of memory array
1 0 0 zero
1 0 1 upper 1/2 of memory array
1 1 0 upper 1/4 of memory array
1 1 1 upper 1/8 of memory array
Figure 33 RCR Mapping in S/W Register Entry
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DQ <15:0>
OM 0 Latency Mode WP 0 WC 0 1 IMP 0 BW Burst Length ^{Control Register}
Operation Mode
D15
opmode
0
sync mode
1 async./ page mode (def)
WAIT# Polarity
D10
polarity
0
active low
1 active high (def)
Latency Mode
D13 D12 D11
latency
000
reserved
001
reserved
010
code2
011
code3 (def)
all others reserved
WAIT# Configuration
D8
timing
0
at delay
1
one data cycle in
advance (def)
Output Impedance
D5
wrap mode
0
full drive (def)
1
1/4 drive
Figure 34 BCR Mapping in S/W Register Entry
Burst Length
D2 D1 D0
length
001
4
010
8
011
16
1 1 1 continuous (def)
all others reserved
Burst Wrap
D3
wrap mode
0
wrap
1
no wrap (def)
Data Sheet
52
V2.0, 2003-12-16