HYE18P32160AC Datasheet, PDF (46/53 Pages) Infineon Technologies AG – 32M Synchronous Burst CellularRAM

HYE18P32160AC(-/L)9.6/12.5/15
32M Synchronous Burst CellularRAM
Functional Description
Table 17 Timing Parameters - Synchronous Read/Write Burst
Parameter
Symbol
9.6
12.5
15
Unit Notes
Min. Max. Min. Max. Min. Max.
Clock period frequency
Lat = 3 f_CLK3
Lat = 2 f_CLK2
Clock period
Lat = 3 t_CLK3
Lat = 2 t_CLK2
Clock high time
t_CKH
Clock low time
t_CKL
Clock rise/fall time
t_T
Input setup time to CLK (except CS) t_SP
Input hold time from CLK
t_HD
ADV pulse width high
t_VPH
ADV pulse width low
t_VP
Burst read 1^st access delay from CLK t_ABA
CS low setup to CLK
t_CSS
Chip select pulse width low time
t_CSL
CS pulse width high
t_CBPH
OE or LB/UB low to output low-Z
t_OL
CS, OE, or LB/UB high to output high-Z t_OD
OE low to output delay
t_AOE
CS low to WAIT valid
t_CWT
CS high to WAIT high-Z
t_WZ
CLK to WAIT valid
t_WK
CLK to output delay
t_ACLK
Output hold from CLK
t_KOH
– 104 –
80
–
–
66
–
50
–
9.6
– 12.5 –
15
15
–
20
–
25
3
–
3.5
–
4
3
–
3.5
–
4
–
1.8
–
2
–
3
–
3.5
–
4
1.5
–
2
–
2
5
–
5
–
7
4
–
4
–
6
–
35
– 46.5 –
3.5 20
4
20
4
–
10
–
10
–
5
–
6
–
8
3
–
3
–
3
0
6
0
8
0
–
20
–
20
–
–
7
–
9
–
0
7
0
8
0
–
7
–
9
–
–
7
–
9
–
2
–
2
–
3
66 MHz –
40 MHz –
– ns –
– ns –
– ns –
– ns –
2 ns –
– ns –
– ns –
–
ns ¹⁾
– ns –
54
ns ²⁾
20
ns ³⁾
10 µs –
– ns –
– ns –
8 ns –
25 ns –
11 ns –
8 ns –
11 ns –
11 ns –
– ns –
1) ADV low for new burst command can not be issued while the previous burst is in burst_init cycle (within latency).
2) In case of refresh collision to the first access, more WAIT cycles will be added.
3) For proper synchronous burst operation, t_CSSmax should be met. Otherwise, it is strongly recommended to use CellularRAM
in asynchronous mode of operation, instead.
2.9
General AC Input/Output Reference Waveform
The input timings refer to a midlevel of V_DDQ/2 while as output timings refer to midlevel V_DDQ/2. The rising and
falling edges are 10 - 90% and < 2 ns.
Data Sheet
46
V2.0, 2003-12-16