HYE18P32160AC Datasheet, PDF (51/53 Pages) Infineon Technologies AG – 32M Synchronous Burst CellularRAM

HYE18P32160AC(-/L)9.6/12.5/15
32M Synchronous Burst CellularRAM
Appendix B: S/W Register Entry Mode (“4-cycle method”)
6
Appendix B: S/W Register Entry Mode (“4-cycle method”)
Other than CRE-controlled SCR operation, CellularRAM supports software (S/W) method as an alternative to
access the control registers. Since S/W register entry mode consists of 4 consecutive access cycles to top memory
location (all addresses are “1”), it is often referred as “4-cycle method”. 4-cycles starts from 2 back-to-back read
cycles (initializing command identification) followed by one write cycle (command identification completed and
which control register is accessed is known), then final write cycle for configuring the selected control register by
the given input or read cycle to check the content of the register through DQ pins. It does function the configuration
of control register bits like the way with dedicated pin, CRE method, but there are a few differences from CRE-
controlled method as follow;
• Register read mode (checking content) is supported with S/W register entry as well as register write (program).
• The mode bits for control register are supplied through DQ <15:0> instead of address pins in CRE-controlled.
Though each register has 21-bits (A<20:0>) for 32M CellularRAM, only low 16-bit registers becomes valid
during S/W method.
• Only asynchronous read and write is allowed for consecutive 4 access cycles to top address. No synchronous
timing is supported. If this entry mode is used in synchronous mode, then clock should stop running and stay
at low level.
• Instead of A19 bit state, the selection of which control register, BCR or RCR, is done with the state of
DQ<15:0> given at 3rd cycle. (“00h” for RCR, “01h” for BCR)
• Since S/W register entry asks for 4 complete access cycles in a row and the device is designed operating with
internally regulated supply which is going to be discharged in deep power-down (DPD) mode, DPD function
is not supported with this programming method.
• The method is realized by the device exactly when 2 consecutive read cycles to top memory location is
followed by write cycle to the same location, so that any exceptional cycle combination - not only access mode,
but also the number of cycles - will fail in invoking the register entry mode properly.
Amax-A0
t_RC
All “1”s
All “1”s
t_WC
All “1”s
ADV#
CS
UB, LB
WE
OE
DQ15-DQ0
(Cycle Type)
(Function)
Read to top memory location (1^st)
Don't Care
Read to top memory location (2nd)
Wait for next write to confirm S/W register entry
0000h(RCR) or 0001h(BCR)
Write to top memory location
Select RCR or BCR
All “_`1”s
Register bits
Write or Read to top memory location
(Write) Configure selected register by DQ inputs
(Read) Output selected register contents through DQ
Figure 32 S/W Register Entry timing (Address input = 1FFFFFh)
Data Sheet
51
V2.0, 2003-12-16