HYE18P32160AC Datasheet, PDF (50/53 Pages) Infineon Technologies AG – 32M Synchronous Burst CellularRAM

HYE18P32160AC(-/L)9.6/12.5/15
32M Synchronous Burst CellularRAM
Appendix A: Low-Frequency Mode
5
Appendix A: Low-Frequency Mode
5.1
Asynchronous Access
Depending on the random access frequency two cases are distinguished:
High Frequency Mode (≥ 100 kHz):
There are no t_RC max. time nor CS/OE max. low time restrictions during subsequent random read or write
accesses.
Low Frequency Mode (< 100 kHz):
There are no t_RC max. time nor CS/OE max. low time restrictions if all control signals (CS, OE, WE, UB/LB) follow
the modified timing as shown below, see attached timing diagram and timing table. There is no extra mode register
setting necessary.
A20-A0
CS
WE
DQ<15:0>
t_ARV
ADDRESS
t_AWV
t_AA
t_WPV
t_DWV
Data Valid
Data Valid
Figure 31 Low-Frequency Mode
Parameter
Address stable time for read access
Address stable overlap with write
pulse
Write pulse width
Data to write time overlap
Symbol
t_ARV
t_AWV
t_WPV
t_DWV
9.6, 12.5
Min.
Max.
70
–
70
–
70
–
70
–
Min.
85
85
15
Max.
–
–
85
–
85
–
Unit Notes
ns
–
ns
–
ns
–
ns
–
Data Sheet
50
V2.0, 2003-12-16