HYE18P32160AC Datasheet, PDF (19/53 Pages) Infineon Technologies AG – 32M Synchronous Burst CellularRAM

HYE18P32160AC(-/L)9.6/12.5/15
32M Synchronous Burst CellularRAM
Functional Description
2.2
Access To The Control Register Map
Write-only access to the control register map is enabled by applying the SCR command asserting the CRE-pin to
high. In combination with CRE set to high, Pin A19 designates the operation to one of either control registers.
Pin A19 set to low selects the Refresh Control Register (RCR), Pin A19 set to high addresses the Bus
Configuration Register (BCR).
Write and read access to the control registers is also available at S/W entry method. For details, please refer to
“Appendix B: S/W Register Entry Mode (“4-cycle method”)” on Page 51.
Bus Control Register BCR
A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 1 0 0 0 OM 0 Latency Mode WP 0 WC 0 1 IMP 0 BW Burst Length
Refresh Control Register RCR
A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 0 0 0 0 0 0 0 0 0 PM TCSR DPD 0
PASR
A19 is the selection address between BCR and RCR
Figure 5 The two Control Registers
All '0' are reserved bits and must be set to zero.
(BCR.A6 has to be set to one)
A20-A0
A19
ADV
OPCODE
Latch OPCODE on Address
Address BCR 0(RCR), 1(BCR)
(Latch Opcode)
CS
UB, LB
WE
CRE
Write Opcode
Initiate Control Register Access
DQx
Don't Care
Figure 6 Control Register Write in SRAM-Type Mode
Data Sheet
19
V2.0, 2003-12-16