HYE18P32160AC Datasheet, PDF (38/53 Pages) Infineon Technologies AG – 32M Synchronous Burst CellularRAM

HYE18P32160AC(-/L)9.6/12.5/15
32M Synchronous Burst CellularRAM
Functional Description
2.7.2 Burst Suspend
While in synchronous burst operation, the bus interface may need to be assigned to other memory transaction
sharing the same bus. Burst suspend mode is used to fulfill this operation. Keeping CS low (WAIT stays asserted
indicating valid data output on DQ pins, though they are tri-stated), burst suspend can be initiated with halted CLK.
CLK can stay at either high or low state.
As specified, duration of keeping CS low can not exceed t_CSL maximum, which is 10 µs, so that internal refresh
operation is able to run properly. In this event of exceeding t_CSL maximum, termination of burst by bringing CS to
high is strongly recommended instead of using burst suspend mode, then reissuing of the discontinued burst
command is required.
CLK
A20-A0
ADV
CS
OE
WE
UB, LB
WA IT
D Q 1 5 -D Q 0
t_CLK
t_SP t_HD
ADR
t_SP
t_{VP H}
t_VP
t_{C SS}
t_ABA
t_SP
t_{H D}
t_AOE
t_OL
Burst Suspend
t_CSL
*1
t_{A O E}
t_{C KL}
t_CKH
t_{H D}
t_CBPH
t_{O D}
Latency Code2
t_CWT
t_WK
Don't C are
t_{A C L K}
Q0
t_{O D}
t_KOH
Q1
Q1
Q2
*1: In case /OE being held low ,
Q 1 is m aintain ed on DQ
/CS low tim e in burst suspend should not exceed 10us
for intern al refresh operation.
t_WZ
Q3
Figure 21 Burst Suspend
Data Sheet
38
V2.0, 2003-12-16