HYE18P32160AC Datasheet, PDF (41/53 Pages) Infineon Technologies AG – 32M Synchronous Burst CellularRAM

HYE18P32160AC(-/L)9.6/12.5/15
32M Synchronous Burst CellularRAM
Functional Description
The programming of control register in NOR-Flash-type mode is performed in the similar manner as asynchronous
write with ADV control except CRE being held high during the code input operation. Note that CRE has to meet
set-up (t_CRS) and hold time (t_CRH) of valid state (= High) in reference to ADV rising edge. ADV may be kept low for
entire operation or go high to latch valid control register information at its rising edge.
CLK
A20-A0
A19
CRE
ADV
CS
t_CKA
t_WC
t_AW
opcode
t_AVS
t_AVH
t_WR
0(RCR), 1(BCR)
t_CRH
t_CRS
t_VPH
t_VP
t_VS
t_CW
ADDRESS
OE
WE
t_WPH
t_WP
UB, LB
DQ15-DQ0
Don't Care
Figure 24 Asynchronous Write To Control Register in NOR-Flash Mode
Table 16 Timing Parameters - Asynchronous Write With ADV Control
Parameter
Symbol
9.6, 12.5
15
Min. Max. Min. Max.
WE high to CLK valid
Write cycle time
Address setup time to write start
Address setup to ADV high
Address hold from ADV high
Address to end of write
ADV pulse width high
ADV pulse width low
ADV setup to end of write
CS to end of write
UB/LB to end of write
Write pulse width low
Write pulse width high
CS high time (synch_read)
t_CKA
t_WC
t_AS
t_AVS
t_AVH
t_AW
t_VPH
t_VP
t_VS
t_CW
t_BW
t_WP
t_WPH
t_CBPH
25
–
35
–
70
–
85
–
0
–
0
–
10
–
10
–
5
–
5
–
70
–
85
–
8
–
10
–
8
–
10
–
70
–
85
–
70
–
85
–
70
–
85
–
40
–
45
–
10
–
15
–
5
–
8
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Data Sheet
41
V2.0, 2003-12-16