HYE18P32160AC Datasheet, PDF (35/53 Pages) Infineon Technologies AG – 32M Synchronous Burst CellularRAM

HYE18P32160AC(-/L)9.6/12.5/15
32M Synchronous Burst CellularRAM
Functional Description
A20-A0
t_VPH
ADV
CS
t_AS
UB, LB
t_WC
ADDRESS
t_AW
t_VS
t_CW
t_BW
t_WR
t_BPH
WE
DQx IN
DQx OUT
t_WP
t_WHZ
t_BLZ, t_LZ
t_DW
t_DH
Data In Valid
High-Z
Don't Care
Figure 18 Asynchronous Write - UB, LB Controlled (OE = V_IH or V_IL, CRE = V_IL)
The programming of control register in SRAM-type mode is performed in the similar manner as asynchronous write
except CRE being held high during the operation. Note that CRE has to meet set-up (t_CRES) and hold time (t_CREH)
of valid state (= High) in reference to WE falling and rising edge, respectively. ADV may be kept low for entire
operation. CS should toggle at the end of the operation to get ready for following access.
A20-A0
A19
t_VPH
ADV
t_WC
OPCODE
t_AW
t_WR
0(RCR), 1(BCR)
CS
t_CW
UB, LB
WE
t_WPH
t_AS
t_WP
CRE
DQx IN
DQx OUT
t_CRES
Don't Care
t_LZ, t_BLZ
t_AW
t_WHZ
t_CREH
High-Z
High-Z
Figure 19 Asynchronous Write to Control Register (OE = V_IH or V_IL)
Data Sheet
35
V2.0, 2003-12-16