HYE18P32160AC Datasheet, PDF (37/53 Pages) Infineon Technologies AG – 32M Synchronous Burst CellularRAM

HYE18P32160AC(-/L)9.6/12.5/15
32M Synchronous Burst CellularRAM
Functional Description
2.7
NOR-Flash-Type Mode
In NOR-Flash mode the CellularRAM applies the NOR-Flash protocol to perform read and write accesses to the
memory. Read accesses can be executed in synchronous burst mode, while write accesses are executed in
asynchronous mode using ADV as address latch strobe signal.
2.7.1 Synchronous Read Mode
[Disclaimer]
WAIT signal of all synchronous timings below is shown in the case of WC=0 (at delay) and WP=0 (active low) though it is not
default state.
In synchronous read mode all operations are referred to the rising or falling clock signal edge. Refresh cycles or
page boundary crossings are indicated by the WAIT output signal which stalls the processor for this period.
CLK
A20-A0
ADV
CS
OE
WE
UB, LB
WAIT
DQ15-DQ0
t_SP t_HD
ADR
t_HD
t_SP
t_VPH t_VP
t_CSS
t_SP t_HD
t_ABA
t_AOE
t_OL
t_CLK
t_CKL
t_CKH
t_HD
t_CBPH
t_OD
Latency Code2
t_CWT
t_WK
t_ACLK
Q0
Q1
Don't Care
in case the burst read access
collides with an ongoing refresh
cycle additional WAIT cycles
might be inserted
t_WZ
t_KOH
Q2
Q3
Q4
While row boundary crossing
occurs, WAIT is asserted
Figure 20 Synchronous Read Burst
Data Sheet
37
V2.0, 2003-12-16