HYE18P32160AC Datasheet, PDF (31/53 Pages) Infineon Technologies AG – 32M Synchronous Burst CellularRAM

HYE18P32160AC(-/L)9.6/12.5/15
32M Synchronous Burst CellularRAM
Functional Description
2.6
SRAM-Type Mode
In SRAM-type mode the CellularRAM applies the standard asynchronous SRAM protocol to perform read and
write accesses.
2.6.1 Asynchronous Read
After power-up the CellularRAM operates per default in asynchronous SRAM-type mode. The synchronous clock
line, CLK has to be held low, while address latch signal, ADV can be held low for entire read and write operation
in this mode or toggled to latch valid address input (refer to “Asynchronous Write with Address Latch (ADV)
Control” on Page 40 for details). WAIT is always asserted as BCR. Bit 10 is programmed, so that the controller
should ignore WAIT during asynchronous mode operation.
Reading from the device in asynchronous mode is accomplished by asserting the Chip Select (CS) and Output
Enable (OE) signals to low while forcing Write Enable (WE) to high. If the Upper Byte (UB) control line is set active
low then the upper word of the addressed data is driven on the output lines, DQ15 to DQ8. If the Lower Byte (LB)
control line is set active low then the lower word of the addressed data is driven on the output lines, DQ7 to DQ0.
The access time is determined by the triggering input - slowest one in low-going transition - among valid address
(t_AA), CS(t_CO), OE(t_OE), UB or LB(t_BA), or ADV(t_AADV).
A20-A0
DQ15-DQ0
t_AA
t_OH
Previous Data
Not Valid
t_RC
ADDRESS
Data Valid
Figure 13 Asynchronous Read - Address Controlled (CS = OE = V_IL, WE = V_IH, UB and/or LB = V_IL,
CRE = V_IL, ADV = V_IL)
A20-A0
ADV
CS
UB, LB
WE
OE
DQ15-DQ0
t_VPH
Don't Care
t_AA
t_AADV
t_CO
t_BA
t_RC
ADDRESS
t_OE
t_LZ^{tBLZ tOLZ}
Data Valid
t_OH
t_CPH
t_BPH
t_BHZ
t_HZ
t_OHZ
Figure 14 Asynchronous Read (WE = V_IH, CRE = V_IL)
Data Sheet
31
V2.0, 2003-12-16