HYE18P32160AC Datasheet, PDF (27/53 Pages) Infineon Technologies AG – 32M Synchronous Burst CellularRAM

HYE18P32160AC(-/L)9.6/12.5/15
32M Synchronous Burst CellularRAM
Functional Description
2.4.1 Latency Modes
The latency mode defines the number of clock cycles which pass before the first output data is valid within a read
burst access (counting from the clock edge where ADV was detected low). The number of inserted wait cycles
increases along with the input clock frequency. Please refer to Table 11 for the proper setting.
Please note that the first access delay might be extended by another 1-3 wait cycles in case the burst read or write
access collides with an ongoing self-refresh operation.
Table 11 Latency Mode Configuration
Latency Mode
-9.6
0
reserved
1
reserved
2
66
3
104
Max. Input Clock Frequency [MHz]
-12.5
-15
reserved
reserved
reserved
reserved
50
40
80
66
CLK
Control
DQx
DQx
DQx
DQx
Read _N NOP
NOP
code0 (reserved)
Q_N+1
Q_N+2
code1 (reserved)
code2
Q_N+1
code3
NOP
Q_N+3
Q_N+2
Q_N+1
NOP
Q_N+4
Q_N+3
Q_N+2
Q_N+1
NOP NOP
Q_N+5
Q_N+6
Q_N+4
Q_N+5
Q_N+3
Q_N+4
Q_N+2
Q_N+3
NOP
Q_N+7
Q_N+6
Q_N+5
Q_N+4
Q_N+7
Q_N+6
Q_N+5
Q_N+7
Q_N+6
Q_N+7
Don't Care
Figure 11 Latency Mode - Functional Diagram
Data Sheet
27
V2.0, 2003-12-16