HYE18P32160AC Datasheet, PDF (32/53 Pages) Infineon Technologies AG – 32M Synchronous Burst CellularRAM

HYE18P32160AC(-/L)9.6/12.5/15
32M Synchronous Burst CellularRAM
Functional Description
2.6.2 Page Mode
If activated by RCR.Bit7 page mode allows to toggle the four lower address bits (A3 to A0) to perform subsequent
random read accesses (max. 16-words by A3 - A0) at much faster speed than 1^st read access. Page mode
operation supports only read access in CellularRAM. As soon as page mode is activated, CS low time restriction
(t_CSL) applies. In case of CS staying low longer than t_CSL limit, then it is alternative way to toggle non-page address
(A20 - A4) no later than t_CSL,max. Therefore the usage of page mode is only recommended in systems which can
respect this limitation. ADV has to be held low for entire page operation.
Please see also application note on Page 50.
A20-A4
A3-A0
CS
UB, LB
WE
OE
DQ15-DQ0
Don't Care
t_RC
ADDRESS
t_AA
t_CO
ADDRESS
t_PC
ADR
ADR
ADR
ADR
t_CSL
t_BLZ
t_OLZ
t_LZ
t_OH
t_PAA
Data
Data
Data
Data
Data
t_HZ
t_BHZ
t_OHZ
Figure 15 Asynchronous Page Read Mode (CRE = V_IL, ADV = V_IL)
Data Sheet
32
V2.0, 2003-12-16