HYE18P32160AC Datasheet, PDF (24/53 Pages) Infineon Technologies AG – 32M Synchronous Burst CellularRAM

HYE18P32160AC(-/L)9.6/12.5/15
32M Synchronous Burst CellularRAM
Functional Description
2.3.5 Page Mode Enable/Disable
In asynchronous operation mode, the user has the option to enable page mode to toggle A0 - A3 in random way
at higher cycle rate (20 ns vs. 70 ns) to lower access times of subsequent reads within 16-word boundary. Write
operation is not supported in the manner of page mode access. In synchronous mode, this option has no effect.
The max. page length is 16 words, so which A0 - A3 is regarded as page-mode address. If the access needs to
cross the boundary of 16-word (any difference in A20 - A4), then it should start over new random access cycle,
which is the same as asynchronous read operation.
Please note that as soon as page mode is enabled the CS low time restriction applies. This means that the CS
signal must not kept low longer than t_CSL = 10 µs. Please refer to Figure 15.
A20 A19 A18
000
Refresh Control Register (RCR)
A8 A7 A6 A5 A4 A3 A2 A1 A0 _{Address Bus}
0 PM TCSR DPD 0
PASR
Control Register
Control Register Select
A19 control reg
0
RCR
1
BCR
Page Mode Bit
A7
page mode
0
disabled (def.)
1
enabled
Deep Power Down Mode
A4
power down
0
enabled
1
disabled (def.)
A20, A18....A8, A3:
reserved, must be set to '0'.
Temperature-Compensated
Self-Refresh
A6 A5 max. case temp.
11
+85°C (def.)
00
+70°C
01
+45°C
10
+15°C
Partial Array Self Refresh
A2 A1 A0 refreshed memory area
0 0 0 entire memory array (def.)
0 0 1 lower 1/2 of memory array
0 1 0 lower 1/4 of memory array
0 1 1 lower 1/8 of memory array
1 0 0 zero
1 0 1 upper 1/2 of memory array
1 1 0 upper 1/4 of memory array
1 1 1 upper 1/8 of memory array
Data Sheet
24
V2.0, 2003-12-16