HYE18P32160AC Datasheet, PDF (34/53 Pages) Infineon Technologies AG – 32M Synchronous Burst CellularRAM

HYE18P32160AC(-/L)9.6/12.5/15
32M Synchronous Burst CellularRAM
Functional Description
2.6.3 Asynchronous Write
Writing to the device in asynchronous SRAM mode is accomplished by asserting the Chip Select (CS) and Write
Enable (WE) signals to low. ADV can be used to latch the address (refer to “Asynchronous Write with Address
Latch (ADV) Control” on Page 40 for details) or simply held low for entire write operation. If the Upper Byte (UB)
control line is set active low then the upper word (DQ15 to DQ8) of the data bus is written to the specified memory
location. If the Lower Byte (LB) control line is set active low then the lower word (DQ7 to DQ0) of the data bus is
written to the specified memory location. Write operation takes place when either one or both UB and LB is
asserted low. The data is latched by the rising edge of either CS, WE, or UB/LB whichever signal comes first.
t_WC
A20-A0
ADDRESS
t_VPH
t_AW
t_WR
ADV
t_VS
CS
t_CW
UB, LB
WE
DQx IN
DQx OUT
t_BW
t_AS
t_WP
t_WPH
t_DW
t_DH
Data Valid
t_WHZ
t_OW
Don't Care
Figure 16 Asynchronous Write - WE Controlled (OE = V_IH or V_IL, CRE = V_IL)
A20-A0
t_VPH
ADV
CS
t_WC
ADDRESS
t_AW
t_VS
t_AS
t_CW
t_WR
t_CPH
UB, LB
t_BW
WE
DQx IN
DQx OUT
t_WP
t_LZ, t_BLZ
t_WHZ
t_DW
t_DH
Data In Valid
High-Z
Don't Care
Figure 17 Asynchronous Write - CS Controlled (OE = V_IH or V_IL, CRE = V_IL)
Data Sheet
34
V2.0, 2003-12-16