HYE18P32160AC Datasheet, PDF (13/53 Pages) Infineon Technologies AG – 32M Synchronous Burst CellularRAM

HYE18P32160AC(-/L)9.6/12.5/15
32M Synchronous Burst CellularRAM
Overview
1.6
Commands
The supported command set depends on the selected operation mode. By default the CellularRAM device is reset
to the asynchronous SRAM-type mode after power-up. To put the device in a different operation mode the Bus
Configuration Register must be programmed first accordingly. The valid control input states and sequences are
listed below for the different operation modes. Other control signal combinations are not supported.
1.6.1 Commands Supported in SRAM-Type Mode
In the SRAM-type operation mode all commands are of asynchronous nature. Table 3 lists the asynchronous
commands supported in SRAM-type mode. CLK has to be held low for entire asynchronous mode operation.
Table 3 Asynchronous Command Table (SRAM-Type Mode)
Operation Mode Power Mode
CS
ADV WE OE
UB/
LB
CRE A19
A20 - A0
DQ15:0
READ
Active
L
L
H
L
L¹⁾ L
V
ADR
DOUT
WRITE
Active
L
L
L
X²⁾ L¹⁾ L
V
ADR
DIN
SET CONTROL Active
REGISTER
L
L
L
X²⁾ X
HL
RCR DIN X
H BCR DIN
NO OPERATION Standby~Active³⁾ L X H H X L X X
High-Z
DESELECT
Standby
HXXXXXXX
High-Z
DPD⁴⁾
Deep Power Down H X X X X X X X
High-Z
1) Table 3 reflects the behaviour if UB and LB are asserted to low. If only either of the signals, UB or LB, is asserted to low
only the corresponding data byte will be output or written (UB enables DQ15 - DQ8, LB enables DQ7 - DQ0).
2) During a write access invoked by WE set to low the OE signal is ignored.
3) Stand-by power mode applies only to the case when CS goes low from DESELECT while no address change occurs.
Toggling address results in active power mode. Also, NO OPERATION from any active power mode by keeping CS low
consumes the power higher than stand-by mode.
4) Deep power down is maintained until control register is re-programmed to disable DPD control bit (RCR Bit 4).
Note: ‘L’ represents a low voltage level, ‘H’ a high voltage level, ‘X’ represents “Don’t Care”, ‘V’ represents “Valid”.
Table 4 Description of Commands (SRAM-Type Mode)
Mode
Description
READ
The READ command is used to perform an asynchronous read cycle. The
signals, UB and LB, define whether only the lower, the upper or the whole 16-bit
word is output.
WRITE
The WRITE command is used to perform an asynchronous write cycle. The data
is latched on the rising edge of either CS, WE, UB, LB, whichever comes first.
The signals, UB and LB, define whether only the lower, the upper or the whole
16-bit word is latched into the CellularRAM.
SET CONTROL REGISTER
The control registers are loaded via the address inputs A19, A15 - A0 performing
an asynchronous write access. Please refer to the control register description for
details. The SCR command can only be issued when the CellularRAM is in idle
state.
NO OPERATION
The NOP command is used to perform a no operation to the CellularRAM, which
is selected (CS = 0). Operations already in progress are not affected. Power
consumption of this command mode varies by address change and initiating
condition.
Data Sheet
13
V2.0, 2003-12-16