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| HYE18P32160AC Datasheet, PDF (45/53 Pages) Infineon Technologies AG – 32M Synchronous Burst CellularRAM | |||
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HYE18P32160AC(-/L)9.6/12.5/15
32M Synchronous Burst CellularRAM
Functional Description
CLK
A20-A0
ADV
CS
OE
WE
tSP tHD
ADR
tVP
tCSS
tSP tHD
tCLK
tCKL
tCKH
tSP tHD
ADR
tCBPH
tVP
tHD
tCSS
tSP tHD
tABA
tAOE
tOL
tHD
tCBPH
tOD
UB, LB
WAIT
DQ15-DQ0
tCWT
Hi-z
tWK
Latency Code2
tHD
Don't Care
D0
D1
D2
D3
tSP
in case the burst write access collides
with an ongoing refresh cycle additional
WAIT cycles might be inserted
tWZ
Latency Code2
tCWT
tWK
tACLK
tWZ
tKOH
Q0
Q1
Q2
Q3
Figure 27 Synchronous Write Burst Followed by Synchronous Read Burst
CLK
A20-A0
tSP tHD
ADR
tCLK
tCKL
tCKH
tSP tHD
ADR
tVP
tVP
ADV
tVPH
tHD
tCBPH
tHD
CS
tABA
tCSS
tOD
tCSS
tAOE
OE
tSP tHD
tOL
tSP tHD
WE
UB, LB
WAIT
Latency Code2
tCWT
tWK
tACLK
tWZ
tCWT
tWK
tKOH
(Hi-z)
Latency Code2
tWZ
tHD
DQ15-DQ0
Q0
Q1
Q2
Q3
D0
D1
D2
D3
Don't Care
tSP
in case the burst access collides with
an ongoing refresh cycle additional
WAIT cycles might be inserted
Figure 28 Synchronous Read Burst Followed by Synchronous Write Burst
Data Sheet
45
V2.0, 2003-12-16
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