HYE18P32160AC Datasheet, PDF (4/53 Pages) Infineon Technologies AG – 32M Synchronous Burst CellularRAM

HYE18P32160AC(-/L)9.6, HYE18P32160AC(-/L)12.5, HYE18P32160AC(-/L)15
Revision History:
2003-12-16
V2.0
Previous Version:
1.8, 1.9 (Target data sheet)
Page
Subjects (major changes since last revision)
all
converted to new datasheet template
all
Addition of part numbered 12.5 which is the combination of 70ns Asynch and 80MHz burst speed
22
change of PASR range setting : remove 3/4, then add 1/8
31-33
remove WAIT timing and parameter definition from asynchronous read
all
2nd bin of Icc2 added. Marking for low-power part puts “L” in the place of “-”
all (synch) No negative (falling) edge of CLK configuration supported
all (synch) ADV hold time from CLK added for burst operation
all (synch) tACLK relaxed to 7ns for grade of 9.6
all (synch) tHD relaxed to 1.5ns for grade of 9.6
all
tLZ, tBLZ, tOLZ are adjusted
all
S/W Register Entry mode is officially supported and specified
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