HYE18P32160AC Datasheet, PDF (25/53 Pages) Infineon Technologies AG – 32M Synchronous Burst CellularRAM

HYE18P32160AC(-/L)9.6/12.5/15
32M Synchronous Burst CellularRAM
Functional Description
2.4
Bus Control Register
The Bus Control Register (BCR) specifies the interface configurations. For the various configuration options
please refer to the register description below. The Bus Control Register is programmed via the Control Register
Set command (with CRE = 1 and A19 = 1) and retains the stored information until it is reprogrammed or the device
loses power.
Please note that the BCR contents can only be set or changed when the CellularRAM is in idle state.
Note: Bit 9 must be set to “0” and bit 6 to “1” for proper operation.
BCR
Bus Control Register
(CRE, A19 = 11_B)
A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
01
0
OM 0 Latency Mode WP 0 WC 0 1 IMP 0 BW Burst Length
Field
RS
OP-
MODE
LAT
Bits
19
15
[13:11}
Type¹⁾ Description
w
Register Select
1 set to 1 to select this BCR (= 0 to select RCR).
w
Operation Mode
The CellularRAM supports three different interface access protocols,
• the SRAM-type protocol with asynchronous read and write accesses
• the NOR-FLASH-type protocol with synchronous read and asynchronous write
accesses
• the FULL SYNCHRONOUS mode with synchronous read and synchronous write
accesses
Operating the device in synchronous mode maximizes bandwidth. The NOR-Flash
type mode is the recommended mode for legacy baseband systems which are not
able to run the synchronous write protocol.
The OPMODE bit defines whether the device is operating in synchronous (fully or
partially) mode or asynchronous mode.
0 NOR-FLASH-type mode
read: synchronous burst mode
write: asynchronous access mode
0 FULL SYNCHRONOUS mode
read: synchronous burst mode
write: synchronous burst mode
The mode of write operation, NOR-FLASH or FULL SYNCHRONOUS, is adaptively
detected:
This is done by detecting a rising clock edge during ADV valid. If a rising clock edge
occurs within ADV valid, FULL SYNCHRONOUS write is detected. If there is no rising
clock edge then NOR FLASH write is detected. Please refer to Figure 22 on Page 40
for asynchronous write and to Figure 25 on Page 43 for synchronous write.
1 SRAM-type mode (default)
read: asynchronous access mode
write: asynchronous access mode
w
Latency Mode
The latency mode has to be adjusted to the desired burst frequency. Depending on
the programmed latency, driving 1^st data output is delayed by the number of clock
cycles as specified in this field counting from the address valid strobe signal, ADV.
010 latency code 2, max 66 MHz burst clock frequency
011 latency code 3 (default), max 104 MHz burst clock frequency
Note: All others reserved.
Data Sheet
25
V2.0, 2003-12-16