HYE18P32160AC Datasheet, PDF (29/53 Pages) Infineon Technologies AG – 32M Synchronous Burst CellularRAM

HYE18P32160AC(-/L)9.6/12.5/15
32M Synchronous Burst CellularRAM
Functional Description
2.4.3 WAIT Signal in Synchronous Burst Mode
The WAIT signal is used in synchronous burst read mode to indicate to the host system when the output data is
invalid. Periods of invalid output data within a burst access might be caused either by first access delays, by delays
induced by row boundary crossings or by self-refresh cycles.
To match with the Flash interfaces of different microprocessor types the polarity and the timing of the WAIT signal
can be configured. The polarity can be programmed to either active low or active high logic. The timing of the WAIT
signal can be adjusted as well. Depending on the BCR setting the WAIT signal will be either asserted at the same
time the data becomes invalid or it will be set active already one clock period in advance.
In asynchronous read mode including page mode, the WAIT signal is not used but always stays asserted as BCR
bit 10 is specified. In this case, system should ignore WAIT state, since it does not reflect any valid information of
data output status.
2.4.4 Hold Data Out Mode
The configuration of Hold Data Out mode is not supported.
Please note that valid data is held always for one clock cycle.
BCR.WP= 0
BCR.HDO= 0
CLK
BCR.WC=1: WAIT
BCR.WC=0: WAIT
DQ15-DQ0
BCR.WP= 0
BCR.HDO= 1
Q0
Q1
Not supported
Q2
Q3
Q4
Q5
Don't care
Figure 12 Data Out Configuration
2.5
Self-Refresh
The CellularRAM relieves the host system from triggering and commanding refresh-operations like it is the case
with conventional DRAMs by performing automatic self-refresh. Self-refresh operations are autonomously
scheduled and performed by the CellularRAM device.
Data Sheet
29
V2.0, 2003-12-16