HYE18P32160AC Datasheet, PDF (30/53 Pages) Infineon Technologies AG – 32M Synchronous Burst CellularRAM

HYE18P32160AC(-/L)9.6/12.5/15
32M Synchronous Burst CellularRAM
Functional Description
Bus Control Register (BCR)
A19 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
1
OM 0 Latency Mode WP 0 WC 0 1 IMP 0 BW Burst Length ^{Control Register}
Control Register Select
A19 control reg
0
selects RCR
1
selects BCR
Operation Mode
A15
opmode
0
sync mode
1 async./ page mode (def)
WAIT Polarity
A10
polarity
0
active low
1 active high (def)
Latency Mode
A13 A12 A11
latency
000
reserved
001
reserved
010
code2
011
code3 (def)
all others reserved
WAIT Configuration
A8
timing
0
at delay
1
one data cycle in
advance (def)
Output Impedance
A5 Drive strength
0
full drive (def)
1
1/4 drive
Burst Length
A2 A1 A0
length
001
4
010
8
011
16
1 1 1 continuous (def)
all others reserved
Burst Wrap
A3
wrap mode
0
wrap
1
no wrap (def)
(note) A9 must be set to “0” for proper operation
(note) A6 must be set to “1” for proper operation
Data Sheet
30
V2.0, 2003-12-16