ICS1531 Datasheet, PDF (69/76 Pages) Integrated Circuit Systems – Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator

ICS1531 Data Sheet - Preliminary
Chapter 10 Timing Diagrams
10.3.3 One-Pixel-per-Clock Mode Timing
For 1-pixel-per-clock mode, Reg 30:6 must be set to ‘1’. Table 10-6 lists time measures for this mode, and
Figure 10-5 shows timing characteristics.
Note: For the 1-pixel-per-clock mode, the ‘B’ channel data outputs are always at ground level.
Table 10-6. Timing for 1-Pixel-per-Clock Mode
Time
Period
Timing Description
Tp, Td CLK Period, CLK Duty Cycle
t1 ACDRCLK Period
t2 ADCRCLK Fall Time to ADCSYNC Rise Time
t3 Digital Data Transition
Min
Typ
Max Units
– See Table 10-3. –
ns
–
t1 = Tp
–
ns
–
TBD
–
ns
0
2.0
2.5 ns
Figure 10-7. AC Timing for 1-Pixel-per-Clock Mode
P+1
P+4
Analog Data In:
ARED
P
P+3
AGRN
ABLUE
Tp, Td
P+2
P+5
CLK
t1
ADCRCLK
t2
ADCSYNC
t3
‘DAa’tCahOauntnpePul-t6Digital
P-5
P-4
P-3
P-2
P-1
P
‘B’ Channel Digital
Data Output
ICS1531 Rev N 12/1/99
Copyright © 1999, Integrated Circuit Systems, Inc.
All rights reserved.
69
December, 1999