ICS1531 Datasheet, PDF (42/76 Pages) Integrated Circuit Systems – Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator

ICS1531 Data Sheet - Preliminary
Chapter 6 Register Set
6.5.23 Register 26h: MCLK-M
The MCLK-M Register is used to divide the reference frequency provided to the MCLK PLL. The ‘M’ value
is used to determine the output frequency of the PLL as specified in the equation given in Section 6.5.24,
“Register 27h: MCLK-N”.
Table 6-23. MCLK-M Register
Bit
Bit Name
26:7- MCLK_M [7-0]
26:0
Bit Definition
Ac- Spec. Re-
cess Func. set
MCLK M (Reference Divider) [7-0].
• This register includes bits for the MCLK Reference
R/W D-MK
0
Divider.
• The value in this register is used as the variable ‘M’ in the
frequency equation given in Section 6.5.24, “Register
27h: MCLK-N”.
6.5.24 Register 27h: MCLK-N
The MCLK-N Register is used to determine the output frequency of the MCLK.
Table 6-24. MCLK-N Register
Bit
Bit Name
27:7- MCLK_N [7-0]
27:0
Bit Definition
Ac- Spec. Re-
cess Func. set
MCLK N (Feedback Divider) [7-0].
• This register includes bits for the MCLK Feedback
R/W D-MK
0
Divider.
• The value in this register is used as the variable ‘N’ in
the frequency equation for the MCLK.
To determine the MCLK frequency (which is in units of MHz), use the following equation:
F_MCLK =
OSC × (N + 8)
(M + 2)
ICS1531 Rev N 12/1/99
Copyright © 1999, Integrated Circuit Systems, Inc.
All rights reserved.
42
December, 1999