ICS1531 Datasheet, PDF (13/76 Pages) Integrated Circuit Systems – Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator

ICS1531 Data Sheet - Preliminary
Chapter 3 Pin Diagram and Listings
3.2.3.2 Control Pins
Table 3-4. Control Pins
Pin
Name
CLAMP
PSEL1,
PSEL2,
PSEL3
TRESET
VSS(TEST)
Pin
Type
Input
Output
Pin Description
Clamp.
This pin accepts an external signal that is provided as an alternative to the ICS1531’s
internally generated clamp signal.
Programmable Select 1, 2, 3.
These pins are used as general-purpose programmable output pins.
Input
Input
Test Reset.
When the ICS1531:
• Is not in Test mode, this pin has no effect.
• Is placed into Test mode:
– This pin acts as a reset that sets the ICS1531 to an initial known state.
– For information about the Test mode, in this table see VSS(TEST).
Ground (Normal Mode) or Test Mode.
• Normal Mode.
For the VSS(TEST) pin’s Normal-mode function, see Table 3-4.
• Test Mode.
– When this pin is connected to either VDDA or VDDAADC, the ICS1531 is in Test
mode. As a result, the ICS1531 is set to an initial known state.
– The Test mode overrides whatever the bit setting of Reg 37:3 is, so that the
Calibration Regs 38h to 3Ch are automatically enabled.
– The Test mode bits are intended for use only by ICS.
ICS1531
VSS(TEST)
VDDA or VDDAADC
Test Mode
In Test mode, Test-mode bits are
enabled and Calibration Regs
38h to 3Ch are automatically
enabled.
ICS1531 Rev N 12/1/99
Copyright © 1999, Integrated Circuit Systems, Inc.
All rights reserved.
13
December, 1999