ICS1531 Datasheet, PDF (51/76 Pages) Integrated Circuit Systems – Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator

ICS1531 Data Sheet - Preliminary
Chapter 6 Register Set
6.5.39 Register 37h: PSEL
The PSEL Register is used to program the general-purpose pins, PSEL1 through PSEL3.
Table 6-38. PSEL Register
Bit
Bit Name
Bit Definition
Ac- Spec. Re-
cess Func. set
37:7 ADCRCLK_Inv ADCRCLK Invert.
This bit inverts the ADCRCLK signal.
• 0 = Do not invert the ADCRCLK signal.
• 1 = Invert the ADCRCLK signal (default).
–
–
1
37:6- ADCRCLK_Del ADCRCLK Delay.
–
37:5
These bits delay the ADCRCLK signal, relative to data, in
0.5-ns increments.
• 0 = 0-ns delay of ADCRCLK
• 1 = 0.5-ns delay of ADCRCLK
• 2 = 1.0-ns delay of ADCRCLK (default)
• 3 = 1.5-ns delay of ADCRCLK
–
2
37:4
Reserved
Reserved.
• See Section 6.1, “Reserved Bits”.
• This bit must be programmed to ‘0’.
–
–
0
37:3
Cal_Access
Calibration Access.
R/W
–
0
Depending on the state of the VSS(TEST) pin (see
Section 3.2.3.6, “Ground Pins”), this bit performs in either
the Normal mode or the Test mode.
• Normal mode.
When the ICS1531 is in Normal mode and this bit =
– 0, Calibration Regs cannot be accessed.
– 1, Calibration Regs 38h to 3Ch can be accessed.
• Test mode.
– When the ICS1531 is in Test mode, Calibration
Regs 38h to 3Ch can be accessed, regardless of
the setting of Reg 37:3.
– The Test mode is intended for use only by ICS.
37:2 PSEL3
Programmable Select 3.
R/W
–
0
This bit is used to program general-purpose pin PSEL3.
37:1 PSEL2
Programmable Select 2.
R/W
–
0
This bit is used to program general-purpose pin PSEL2.
37:0 PSEL1
Programmable Select 1.
R/W
–
0
This bit is used to program general-purpose pin PSEL1.
ICS1531 Rev N 12/1/99
Copyright © 1999, Integrated Circuit Systems, Inc.
All rights reserved.
51
December, 1999