ICS1531 Datasheet, PDF (38/76 Pages) Integrated Circuit Systems – Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator

ICS1531 Data Sheet - Preliminary
Chapter 6 Register Set
6.5.17 Register 20h: PNLCLK-M
The PNLCLK-M Register is used to divide the reference frequency provided to the PNLCLK PLL. The ‘M’
value is used to determine the output frequency of the PLL as specified in the equation given in Section
6.5.18, “Register 21h: PNLCLK-N”.
Table 6-17. PNLCLK-M Register
Bit
Bit Name
Bit Definition
Ac- Spec. Re-
cess Func. set
20:7- PNLCLK_M [7-0] PNLCLK_M (Reference Divider) [7-0].
20:0
• This register includes bits for the PNLCLK Reference
R/W D-PK
0
Divider.
• The value in this register is used as the variable ‘M’ in the
frequency equation given in Section 6.5.18, “Register
21h: PNLCLK-N”.
6.5.18 Register 21h: PNLCLK-N
The PNLCLK-N Register is used to determine the output frequency of the PNLCLK.
Table 6-18. PNLCLK-N Register
Bit
Bit Name
Bit Definition
Ac- Spec. Re-
cess Func. set
21:7- PNLCLK_N [7-0] PNLCLK_N (Feedback Divider) [7-0].
21:0
• This register includes bits for the PNLCLK Feedback
R/W D-PK
0
Divider.
• The value in this register is used as the variable ‘N’ in the
frequency equation for the PNLCLK.
To determine the PNLCLK frequency (which is in units of MHz), use the following equation:
F_PNLCLK =
OSC × (N + 8)
(M + 2)
ICS1531 Rev N 12/1/99
Copyright © 1999, Integrated Circuit Systems, Inc.
All rights reserved.
38
December, 1999