ICS1531 Datasheet, PDF (33/76 Pages) Integrated Circuit Systems – Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator

ICS1531 Data Sheet - Preliminary
Chapter 6 Register Set
6.5.7 Register 06h: Output Enables
The Output Enables Register is used to select and enable various outputs.
Note:
Table 6-10 refers to ADC_FUNC, an internally generated signal that is delayed so it is in the same
domain as the internal ADC_CLK signal (that is, the pixel clock). Functionally, depending on the
setting of Reg 06:3, ADC_FUNC is equivalent to either ADCSYNC (which provides recovered
HSYNC) or the input HSYNC.
Table 6-10. Output Enables Register
Bit Bit Name
Bit Definition
Ac- Spec. Re-
cess Func. set
06:7 Reserved
Reserved.
• See Section 6.1, “Reserved Bits”.
• This bit can be programmed to ‘0’.
–
–
0
06:6 OE_Tck
Output Enable Clock.
–
–
0
This bit enables the pixel clock output on the CLK pin.
• 0 = The pixel clock output is disabled (high- impedance).
• 1 = The pixel clock output is enabled.
06:5 OE_ADCRCLK Output Enable for ADCRCLK.
–
–
0
This bit enables the clock output for ADCRCLK. When this bit is:
• 0 = The following are both true:
– The clock output for the ADC is disabled (that is, high-
impedance).
– Because the clock source for the ADC is accepted from
the ADCRCLK pin, an external clock can be provided to
the ADC.
• 1 = The following are both true:
– The clock output for the ADC is enabled.
– The input multiplexer selects the internal pixel clock.
06:4 OE_ADCSYNC Output Enable for ADCSYNC.
R/W
–
0
This bit enables the output for ADCSYNC. When this bit is:
• 0 = The following are both true:
– The output for the ADCSYNC signal is disabled (high-
impedance).
– An external sync signal for the ADC is accepted from the
ADCSYNC pin.
• 1 = The following are both true:
– The output for the ADCSYNC signal is enabled.
– The input multiplexer selects the internal sync signal.
06:3 FUNC_Sel
FUNC Select.
–
–
0
This bit selects the source of the signal to ADC_FUNC. (See the
note at the first of this table.)
• 0 = The source is recovered HSYNC.
• 1 = The source is REF, the input HYSNC signal that is
conditioned before it goes to the phase-locked loop block.
ICS1531 Rev N 12/1/99
Copyright © 1999, Integrated Circuit Systems, Inc.
All rights reserved.
33
December, 1999