ICS1531 Datasheet, PDF (37/76 Pages) Integrated Circuit Systems – Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator

ICS1531 Data Sheet - Preliminary
Chapter 6 Register Set
6.5.15 Register 12h: Rd_Reg
The Rd_Reg (Read Register) is used to read the lock status of the four PLLs on the ICS1531.
Table 6-16. Rd_Reg Register
Bit
Bit Name
Bit Definition
12:7- Reserved
12:4
12:3 PNLCLK_Lock
12:2 MCLK_Lock
12:1 Pixel PLL_Lock
12:0 DPA_Lock
Reserved.
Because these bits are read-only:
• These bits cannot be programmed.
• Information on these bits can be ignored.
PNLCLK Lock (Status).
• 0 = The PNLCLK is ‘unlocked’.
• 1 = The PNLCLK is ‘locked’.
MCLK Lock (Status).
• 0 = The MCLK is ‘unlocked’.
• 1 = The MCLK is ‘locked’.
Pixel Phase-Locked Loop Lock (Status).
• 0 = The pixel PLL is ‘unlocked’.
• 1 = The pixel PLL is ‘locked’.
Dynamic Phase Adjust Lock (Status).
• 0 = The DPA is ‘unlocked’.
• 1 = The DPA is ‘locked’.
Ac- Spec. Re-
cess Func. set
Read –
N/A
Read –
N/A
Read –
N/A
Read –
N/A
Read –
N/A
6.5.16 Register 13h-1Fh: Reserved
These registers are reserved. (See Section 6.1, “Reserved Bits”.)
ICS1531 Rev N 12/1/99
Copyright © 1999, Integrated Circuit Systems, Inc.
All rights reserved.
37
December, 1999