ICS1531 Datasheet, PDF (41/76 Pages) Integrated Circuit Systems – Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator

ICS1531 Data Sheet - Preliminary
Chapter 6 Register Set
6.5.22 Register 25h: PNLCLK-OE
The PNLCLK-OE (PNLCLK Output Enable) Register is used to enable the PNLCLK output and
spread-spectrum functionality. (To select values, see Section 7.3, “Programming Spread Spectrum”.)
Table 6-22. PNLCLK-OE Register
Bit
Bit Name
Bit Definition
25:7-
25:3
25:2
25:1
25:0
Reserved
CLK_SEL
PNLCLK_SSENB
PNLCLK_OE
Reserved.
• See Section 6.1, “Reserved Bits”.
• These bits can be programmed to ‘0’.
Clock Selection.
This bit selects the input to the PNLCLK phase-lock loop.
• 0 = Frequency input is from a crystal.
• 1 = Frequency input is from ADC_CLK, divided by 16.
PNLCLK Spread-Spectrum Enable.
• 0 = Disable PNLCLK spread-spectrum functionality.
• 1 = Enable PNLCLK spread-spectrum functionality.
PNLCLK Output Enable.
• 0 = Disable PNLCLK output.
• 1 = Enable PNLCLK output.
Ac- Spec. Re-
cess Func. set
–
–
0
R/W
–
0
R/W
–
0
R/W
–
0
ICS1531 Rev N 12/1/99
Copyright © 1999, Integrated Circuit Systems, Inc.
All rights reserved.
41
December, 1999