ICS1531 Datasheet, PDF (5/76 Pages) Integrated Circuit Systems – Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator

ICS1531 Data Sheet - Preliminary
Chapter 2 Summary
2.3 Phase-Locked Loop (Generates Pixel Clock from Input HSYNC)
The ICS1531 uses a phase-locked loop (PLL) to generate its pixel clock output frequency. A PLL is a
closed-loop feedback system that locks an output signal’s phase and frequency to that of a reference input
signal’s phase and frequency. In the case of the ICS1531, when its PLL is locked it locks a pixel clock
output to that of an HSYNC signal from input video.For a block diagram of the ICS1531 PLL, see Figure 4-1
and Figure 4-2.
2.3.1 Phase/Frequency Detector (Compares Two Input Signals)
The first section of the PLL is the Phase/Frequency Detector (PFD). To use the PLL, first the PFD must be
enabled either through hardware control (with a signal from the PDEN pin) or software control (Reg 00:1-0).
Once the PFD is enabled, the PFD compares both the phase and frequency of the following two input
signals.
• PFD Input Signal 1: External HSYNC Signal or Internal Oscillator Signal
The first input to the PFD can be selected from either the external HSYNC signal or the ICS1531 internal
crystal oscillator signal (Reg 00:5).
– External HSYNC signal
Typically, one of the input signals to the PFD comes from the HSYNC of a PC display controller. This
input HSYNC signal can have a transition time of tens of nanoseconds. Furthermore, if the input
HSYNC signal is from a remote source, its pulses can degrade.
A high-performance Schmitt trigger (Reg 00:7-6) conditions the HSYNC pulse before it is input to the
PFD. The polarity of this input pulse can be programmed (Reg 00:2). The result of this conditioning
is REF, a clean reference clock signal that in comparison to the input HSYNC signal has a short
transition time. [For more information on adjusting the HSYNC signal, see Section 2.6, “Dynamic
Phase Adjust (Positions Pixel Clock on Sub-Pixel Basis)”.]
– Internal crystal oscillator
Alternatively, one of the input signals to the PFD can be from the ICS1531 internal crystal oscillator
(Regs 07:7-0 and 2C:6-4).
• PFD Input Signal 2: Signal from Feedback Loop
The second input to the PFD comes from the output of the PLL feedback loop, which results from the
processing that takes place with the charge pump, filter, voltage-controlled oscillator, post-scaler divider,
and feedback divider. That is, the PLL output (the signal from the feedback loop) also appears as one of
the two inputs to the PFD.
As a result of the comparison of the two input signals, the PFD processes the inputs so there is the proper
ratio between them. Then the PFD uses the output to drive a charge pump.
2.3.2 Charge Pump (Boosts Voltage Gain of Signal from PFD)
The charge pump, which is a current-source and current-sink pair, boosts the voltage gain of the signal
from the PFD. This PFD signal gain is programmable over a 7-bit range up to 128 µA (Reg 01:2-0).
2.3.3 Loop Filter (Filters Output from Charge Pump)
The loop filter, which is a capacitance and resistance in series, acts as a low-bandpass filter for the
frequency output from the charge pump. The ICS1531 can select between either an external loop filter, or
more typically, an internal loop filter (Reg 08:0). The advantage of the internal filter is that it can be used for
all Video Electronics Standards Association (VESA) timing modes, for ease in manufacturing.
Note:
VESA establishes standard timing specifications for the personal-computer industry. Although
many computer manufacturers require that display controllers adhere to the VESA timing
specifications, there is no enforcement. As a result, not all display controllers conform precisely
to the VESA timing specifications.
ICS1531 Rev N 12/1/99
Copyright © 1999, Integrated Circuit Systems, Inc.
All rights reserved.
December, 1999
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