ICS1531 Datasheet, PDF (28/76 Pages) Integrated Circuit Systems – Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator

ICS1531 Data Sheet - Preliminary
Chapter 6 Register Set
6.5 Register Definitions
The tables in this section specify for each register bit the reset value, if one exists. After a reset, the
ICS1531 sets all register bits to their default values.
Note:
1. For the reserved bits, see Section 6.1, “Reserved Bits”.
2. For Register Set conventions, see Section 6.2, “Register Set Conventions”.
3. For acronyms used in this table, see Section 6.3, “Register Set Abbreviations and Acronyms”.
6.5.1 Register 00h: Input Control Register
The Input Control Register is used to select inputs that control the pixel PLL Phase/Frequency Detector.
Table 6-3. Input Control Register
Bit
Bit Name
Bit Definition
00:7-
00:6
HSYNC_Sel [1-0]
Horizontal Sync Select [1-0].
These multiplexed bits select one of possible four Schmitt
triggers that connect to the input HSYNC pin.
• 0 = Schmitt trigger 0
• 1 = Schmitt trigger 1
• 2 = Schmitt trigger 2. (Recommended setting.)
• 3 = Schmitt trigger 3
00:5 In_Sel
Input Select.
This bit selects an input to the Phase/Frequency Detector.
• 0 = The input is HSYNC.
• 1 = The input is OSC (default).
00:4 Fdbk Div Load
Feedback Divider Load Control.
This bit selects a load for the internal feedback divider.
• 0 = The load is on the pixel PLL reset.
• 1 = The load is on the next scan line.
00:3 Fdbk_Pol
Feedback Polarity.
This bit selects the polarity of the feedback signal to the
Phase/ Frequency Detector.
• 0 = The polarity is positive edge.
• 1 = The polarity is negative edge.
00:2 Ref_Pol
(External) Reference Polarity.
This bit selects the polarity of REF, the reference signal
provided by the input HSYNC to the Phase/Frequency
Detector.
• 0 = The polarity is positive edge.
• 1 = The polarity is negative edge.
00:1 PD_Pol
Phase/(Frequency) Detector Polarity.
This bit selects the polarity of the PDEN signal to the
Phase/Frequency Detector.
• 0 = The signal from the PDEN pin is active high.
• 1 = The signal from the PDEN pin is active low.
Note: This bit is disabled when Reg 00:0 = 1.
Ac- Spec. Re-
cess Func. set
–
–
0
–
–
1
R/W
–
0
R/W
–
0
R/W
–
0
R/W
–
0
ICS1531 Rev N 12/1/99
Copyright © 1999, Integrated Circuit Systems, Inc.
All rights reserved.
28
December, 1999