ICS1531 Datasheet, PDF (40/76 Pages) Integrated Circuit Systems – Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator

ICS1531 Data Sheet - Preliminary
Chapter 6 Register Set
6.5.21 Register 24h: PNLCLK-SSOE
The PNLCLK-SSOE (PNLCLK Spread-Spectrum Output Enable) Register is used to control the gain of the
PNLCLK PFD and spread spectrum. (To select values, see Section 7.3, “Programming Spread Spectrum”.)
Table 6-21. PNLCLK-SSOE Register
Bit
Bit Name
24:7- PNLCLK_SS
24:6 [1-0]
24:5 Reserved
24:4- PNLCLK_PFD
24:2 [2-0]
24:1- PNLCLK_OSD
24:0 [1-0]
Bit Definition
Ac- Spec. Re-
cess Func. set
PNLCLK Spread-Spectrum (Gain Select) [1-0].
R/W D-PK
0
These bits determine the PNLCLK spread-spectrum gain.
• 0 = The gain is 1.
• 1 = The gain is 2.
• 2 = The gain is 4.
• 3 = The gain is 8.
Reserved.
• See Section 6.1, “Reserved Bits”.
• This bit can be programmed to ‘0’.
–
–
0
PNLCLK Phase/Frequency Detector (Gain Select) [2-0]. R/W D-PK
0
These bits determine the PNLCLK Phase/Frequency
Detector gain.
• 0 = The gain is 1.
• 1 = The gain is 2.
• 2 = The gain is 4.
• 3 = The gain is 8.
• 4 = The gain is 16, and so forth.
PNLCLK Output Scaler Divider (Value) [1-0].
These bits determine the value for dividing the PNLCLK
output scaler as follows:
• 0 = Division is by 1.
• 1 = Division is by 2.
• 2 = Division is by 4.
• 3 = Division is by 8.
R/W D-PK
0
ICS1531 Rev N 12/1/99
Copyright © 1999, Integrated Circuit Systems, Inc.
All rights reserved.
40
December, 1999