ICS1531 Datasheet, PDF (55/76 Pages) Integrated Circuit Systems – Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator

ICS1531 Data Sheet - Preliminary
7.2 Programming Flow for Modifying PLL and DPA Settings
Figure 7-2. ICS1531 Flow for Capture/Input Clock PLL
Initialize
Registers 0 and 8
Set DPA Output
Delay to 0
Reg4[5:0]=0
Chapter 7 Programming
No Change Yes
PLL Freq.
?
Set Input, PFD Gain, Post
Scaler, and Feedback Divider
Regs 0 through 3
PLL Software Reset
Wait ~ 1ms
RegA=50h
Set DPA
Resolution
No
PLL
Locked
?
Yes
DPA Software Reset RegA=0Ah
Wait ~ 1ms
Reg12[1]=1?
Select Desired
DPA Output Delay
Reg4[5:0]
Enable
Desired Outputs
Reg6[6:2]
Done
ICS1531 Rev N 12/1/99
Copyright © 1999, Integrated Circuit Systems, Inc.
All rights reserved.
55
December, 1999