ICS1531 Datasheet, PDF (66/76 Pages) Integrated Circuit Systems – Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator

ICS1531 Data Sheet - Preliminary
Chapter 10 Timing Diagrams
10.2 Power-On Reset Timing
Table 10-2 lists typical ICS1531 power-on reset (POR) timing measures and Figure 10-4 shows the POR
timing relationships. (For information on how the ICS1531 POR circuitry operates, see Section 8.2, “Power
Considerations”.)
Table 10-2. Typical ICS1531 POR Transition Times
Symbol
VDD
VDD_th
t₁
Timing Description
Supply Voltage (‘On’ State)
Threshold Supply Voltage
Hold Time for Reset State
Min
Typ
Max
Units
3.0
3.3
3.6
V
–
1.8
–
V
–
10
–
ms
If a reset:
• Is desired, reduce the VDD supply voltage (and the voltage on all ICS1531 pins) so that it is below the
threshold voltage (VDD_th) of the POR circuit for the period t1. (A time of 10 ms is sufficient.)
• Is not desired, ensure either one or both of the following conditions:
– Ensure the VDD supply voltage (and the voltage on all ICS1531 pins) is not reduced below V_min.
– If the VDD supply voltage (and the voltage on all ICS1531 pins) is reduced below V_th, then ensure
that it is at this level for less than the period t1.
Note: The POR signal is an internal signal. It is generated regardless of the ICS1531 mode.
Figure 10-4. Power-On Reset Condition for ICS1531
VDD_min
VDD_th
t₁
ICS1531 Rev N 12/1/99
Copyright © 1999, Integrated Circuit Systems, Inc.
All rights reserved.
66
December, 1999