ICS1531 Datasheet, PDF (27/76 Pages) Integrated Circuit Systems – Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator

ICS1531 Data Sheet - Preliminary
Chapter 6 Register Set
Table 6-2. Register Set Outline (Continued)
Register Register Name Register
Index
Access
3Ah
B_COMP_OFF R/W
Bit # Bit Name
7-4 B_C_O_B
3-0 B_C_O_A
Brief Description
Select blue comparator offset, ‘B’ channel
Select blue comparator offset, ‘A’ channel
Reset
Value
7
7
3Bh
CAL_1
R/W
7 Reserved
6 ADC_DD
5-3 G_CD
2-0 R_CD
Reserved
0
Select delay for all RGB data from ADC (LSB, bit 0)
0
Select clock delay for green channel
5
Select clock delay for red channel
5
3Ch
CAL_2
R/W
7-5 Bandgap_CAL Calibrate bandgap voltage
5
4-3 ADC_DD
Select delay for all RGB data from ADC (MSB bits 2-1) 0
2-0 B_CD
Select clock delay for blue channel
5
ICS1531 Rev N 12/1/99
Copyright © 1999, Integrated Circuit Systems, Inc.
All rights reserved.
27
December, 1999