ICS1531 Datasheet, PDF (39/76 Pages) Integrated Circuit Systems – Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator

ICS1531 Data Sheet - Preliminary
Chapter 6 Register Set
6.5.19 Register 22h: PNLCLK-SS0
The PNLCLK-SS0 (PNLCLK Spread-Spectrum Counter 0) Register is used in combination with the
PNLCLK-SS1 Register to specify the amount of clock spread. (To select values, see Section 7.3,
“Programming Spread Spectrum”.)
Table 6-19. PNLCLK-SS0 Register
Bit
Bit Name
22:7- PNLCLK_SS0
22:0 [7-0]
Bit Definition
Ac- Spec. Re-
cess Func. set
PNLCLK Spread-Spectrum (Counter) 0 [7-0].
R/W D-PK
0
These bits are the least-significant bits [7-0] for the PNLCLK
spread-spectrum counter.
6.5.20 Register 23h: PNLCLK-SS1
The PNLCLK-SS1 (PNLCLK Spread-Spectrum Counter 1) Register is used in combination with the
PNLCLK-SS0 Register. (To select values, see Section 7.3, “Programming Spread Spectrum”.)
Table 6-20. PNLCLK-SS1 Register
Bit
Bit Name
23:7- Reserved
23:4
23:3- PNLCLK_SS1
23:0 [3-0]
Bit Definition
Ac- Spec. Re-
cess Func. set
Reserved.
• See Section 6.1, “Reserved Bits”.
• These bits can be programmed to ‘0’.
–
–
0
PNLCLK Spread-Spectrum (Counter) 1 [3-0].
R/W D-PK
0
These bits are the most-significant bits [11-8] for the PNLCLK
spread-spectrum counter.
ICS1531 Rev N 12/1/99
Copyright © 1999, Integrated Circuit Systems, Inc.
All rights reserved.
39
December, 1999