ICS1531 Datasheet, PDF (60/76 Pages) Integrated Circuit Systems – Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator

ICS1531 Data Sheet - Preliminary
Chapter 8 Layout and Power Considerations
8.2 Power Considerations
8.2.1 Power-On Reset
The ICS1531 incorporates special internal power-on reset circuitry that requires no external reset signal
connections.
• During normal operations, the VDD supply voltage for the ICS1531 must remain within the
recommended operating conditions. (See Section 9.2, “Recommended Operating Conditions”.)
• To reset the ICS1531, do the following:
– Reduce the level of the VDD supply voltage to the ICS1531 (and the voltage seen on all ICS1531
pins) so that it is below V_th, the threshold voltage for time t1. (For a typical threshold voltage V_th, see
Section 10.2, “Power-On Reset Timing”.)
– Keep the supply voltage below that threshold voltage for time t1, such that power-conditioning
capacitors for the printed circuit board are drained and the proper reset state is latched. (For a typical
time t1, see Section 10.2, “Power-On Reset Timing”.)
• A successful power-on reset results in all the ICS1531 registers having the appropriate reset values as
stated in the tables in Chapter 6, “Register Set”.
8.2.2 Power Conservation
For information on how to conserve power, see the ICS1531 application notes.
8.2.3 Layout for Power Supply Voltages
See Section 8.1.1, “General Guidelines for Printed Circuit Board Layout”.
ICS1531 Rev N 12/1/99
Copyright © 1999, Integrated Circuit Systems, Inc.
All rights reserved.
60
December, 1999