ICS1531 Datasheet, PDF (46/76 Pages) Integrated Circuit Systems – Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator

ICS1531 Data Sheet - Preliminary
Chapter 6 Register Set
6.5.30 Register 2Dh: PLL Reset
The PLL Reset (Phase-Locked Loop Reset) Register is used to reset the MCLK and PNLCLK PLLs.
Table 6-30. PLL Reset Register
Bit
Bit Name
Bit Definition
2D:7- MCLK_Reset [3-0]
2D:4
MCLK Reset [3-0].
Writing 5xh to these bits:
• Resets MCLK PLL.
• Loads working Regs 26h to 2Bh.
2D:3-
2D:0
PNLCLK_Reset [3-0]
PNLCLK Reset [3-0].
Writing xAh to these bits:
• Resets PNLCLK PLL.
• Loads working Regs 20h to 25h.
Ac- Spec. Re-
cess Func. set
Write
–
N/A
Write
–
N/A
6.5.31 Register 2Eh-2Fh: Reserved
These registers are reserved. (See Section 6.1, “Reserved Bits”.)
ICS1531 Rev N 12/1/99
Copyright © 1999, Integrated Circuit Systems, Inc.
All rights reserved.
46
December, 1999