ICS1531 Datasheet, PDF (53/76 Pages) Integrated Circuit Systems – Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator

ICS1531 Data Sheet - Preliminary
Chapter 6 Register Set
6.5.40.4 Register 3Bh: CAL_1
The CAL_1 Register is used to select (1) delays to calibrate the ADC data delay and (2) the clock delay for
the green and red channels.
Table 6-42. CAL1 Register
Bit Bit Name
Bit Definition
Ac- Spec. Re-
cess Func. set
3B:7 Reserved
Reserved.
• See Section 6.1, “Reserved Bits”.
• This bit can be programmed to ‘0’.
–
–
0
3B:6 ADC_DD [0] Analog-to-Digital Converter Data (Global) Delay [0].
See Reg –
0
• This bit works with Regs 3C:4 and 3C:3 for a global delay 37:3
of all RGB data output from the ADC.
• This bit is the least-significant bit.
3B:5-
3B:3
G_CD
Green (Channel) Clock Delay.
R/W
–
5
These bits select a delay (that is, an offset) for use in
calibrating the clock for the green channel. (An acknowledge See Reg
of these bits occurs only when the Calibration Regs are
37:3
enabled.) When these bits are:
• 0, the clock delay calibration offset is 0.
• 1 or above, the clock delay calibration offset increases.
3B:2
3B:0
R_CD
Red (Channel) Clock Delay.
R/W
–
5
These bits select a delay (that is, an offset) for use in
calibrating the clock for the red channel. (An acknowledge of See Reg
these bits occurs only when the Calibration Regs are
37:3
enabled.) When these bits are:
• 0, the clock delay calibration offset is 0.
• 1 or above, the clock delay calibration offset increases.
6.5.40.5 Register 3Ch: CAL_2
The CAL_2 Register is used to select (1) delays to calibrate the ADC data delay and (2) the clock delay for
blue channel.
Table 6-43. CAL2 Register
Bit
3C:7-
3C:5
3C:4-
3C:3
3C:2-
3C:0
Bit Name
Bit Definition
Ac- Spec. Re-
cess Func. set
Bandgap_CAL Bandgap Calibration.
R/W
–
5
To calibrate the ICS1531 bandgap voltage, these bits adjust
the current to VRTR, VRTG, and VRTB. (An acknowledge
occurs only when the Test mode is enabled.)
ADC_DD [2-1] Analog-to-Digital Converter Data (Global) Delay [2-1]. See Reg –
0
• These bits work with Reg 3B:6 for a global delay of all
37:3
RGB data output from the ADC.
• These bits are the most-significant bits.
B_CD
Blue (Channel) Clock Delay.
R/W
–
5
These bits select a delay (that is, an offset) for use in
calibrating the clock for the blue channel. (An acknowledge See Reg
of these bits occurs only when the Calibration Regs are
37:3
enabled.) When these bits are:
• 0, the clock delay calibration offset is 0.
• 1 or above, the clock delay calibration offset increases.
ICS1531 Rev N 12/1/99
Copyright © 1999, Integrated Circuit Systems, Inc.
All rights reserved.
53
December, 1999