ICS1531 Datasheet, PDF(24/76 Page) Integrated Circuit Systems – Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator

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ICS1531 Datasheet, PDF (24/76 Pages) Integrated Circuit Systems – Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator

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ICS1531 Data Sheet - Preliminary

Chapter 6 Register Set

6.4 Register Set Outline

Table 6-2 outlines the ICS1531 Register Set.

Note:

1. For the reserved bits, see Section 6.1, âReserved Bitsâ.

2. For abbreviations and acronyms, see Section 6.3, âRegister Set Abbreviations and Acronymsâ.

Table 6-2. Register Set Outline

Index

Access

00h

Input Control R/W

Bit # Bit Name

7-6 HSYNC_Sel

5 In_Sel

4 Fdbk Div Load

3 Fdbk_Pol

2 Ref_Pol

1 PD_Pol

0 PD_En

Brief Description

Select a Schmitt trigger

Select input

Select load for Feedback Divider

Select polarity of feedback to Phase/Frequency

Detector

Select polarity of external reference

Select polarity of PDEN to Phase/Frequency Detector

Enable Phase/Frequency Detector

Reset

Value

01h

Loop Control R/W. D-PLL. 7-6 Reserved

Reserved

5-4 PSD

Select value for Post-Scaler Divider

3 Reserved

Reserved

2-0 PFD

Select Phase/Frequency Detector gain

02h

Fdbk Div 0

R/W. D-PLL. 7-0 FDBK [7-0]

Select value for Feedback Divider LSBs bits 7-0

03h

Fdbk Div 1

R/W. D-PLL. 7-4 Reserved

Reserved

3-0 FDBK [11-8]

Select value for Feedback Divider MSBs bits 11-8

04h

DPA Offset

R/W

7-6 Reserved

Reserved

5-0 DPA_OS

Select offset for Dynamic Phase Adjust

05h

DPA Control R/W. D-DPA. 7-2 Reserved

Reserved

1-0 DPA_Res

Select resolution for Dynamic Phase Adjust

06h

Output Enables R/W

7 Reserved

Reserved

6 OE_Tck

Enable clock output to ADC

5 OE_ADCRCLK Enable clock output from ADC

4 OE_ADCSYNC Enable output for delayed ADCSYNC

3 FUNC_Sel

Select signal source for ADC_FUNC signal

2 FUNC_Delay

Select delay for ADC_FUNC signal

1-0 Reserved

Reserved

07h

OSC Divider R/W

7-0 OSC_Div

Specify value for oscillator divider

08h

Internal Filter R/W

7 Shunt_Sel

Select internal filter shunt capacitor size

6-4 Res_Sel

Select internal filter resistor size

3-1 Cap_Sel

Select internal filter capacitor size

0 Fil_Sel

Select type of loop filter

09h

Reserved

N/A

0Ah

Pixel PLL

Write

Reset/

DPA Reset

7-4 Pixel PLL Reset Writing 5xh resets pixel PLL and loads working Regs N/A

1h through 3h

3-0 DPA Reset

Writing xAh resets DPA and loads working Reg 5h

N/A

0Bh-0Fh Reserved

N/A

ICS1531 Rev N 12/1/99

December, 1999

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