ICS1531 Datasheet, PDF (43/76 Pages) Integrated Circuit Systems – Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator

ICS1531 Data Sheet - Preliminary
Chapter 6 Register Set
6.5.25 Register 28h: MCLK-SS0
The MCLK-SS0 (MCLK Spread-Spectrum Counter 0) Register is used in combination with the MCLK-SS1
Register to specify the amount of clock spread. (To select values, see Section 7.3, “Programming Spread
Spectrum”.)
Table 6-25. MCLK-SS0 Register
Bit
Bit Name
Bit Definition
28:7- MCLK_SS0 [7-0]
28:0
MCLK Spread-Spectrum (Counter) 0 [7-0].
These bits are the least-significant bits [7-0] for the MCLK
spread-spectrum counter.
Ac- Spec. Re-
cess Func. set
R/W D-MK
0
6.5.26 Register 29h: MCLK-SS1
The MCLK-SS1 (MCLK Spread-Spectrum Counter 1) Register is used in combination with the MCLK-SS0
Register. (To select values, see Section 7.3, “Programming Spread Spectrum”.)
Table 6-26. MCLK-SS1 Register
Bit
Bit Name
Bit Definition
Ac- Spec. Re-
cess Func. set
29:7- Reserved
29:4
Reserved.
• See Section 6.1, “Reserved Bits”.
• These bits can be programmed to ‘0’.
–
–
0
29:3- MCLK_SS1 [3-0] MCLK Spread-Spectrum (Counter) 1 [3-0].
R/W D-MK
0
29:0
These bits are the most-significant bits [11-8] for the MCLK
spread-spectrum counter.
ICS1531 Rev N 12/1/99
Copyright © 1999, Integrated Circuit Systems, Inc.
All rights reserved.
43
December, 1999