ICS1531 Datasheet, PDF (68/76 Pages) Integrated Circuit Systems – Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator

ICS1531 Data Sheet - Preliminary
Chapter 10 Timing Diagrams
10.3.2 Two-Pixels-per-Clock Mode Timing
For 2-pixels-per-clock mode, Reg 30:6 must be cleared to ‘0’. Table 10-4 lists pixel characteristics for this
mode, as determined by Reg 2:0. (Both ‘A’ and ‘B’ channel pixels are pipelined and aligned with the rising
edge of the ADCRCLK.) Table 10-5 lists time measures for this mode, and Figure 10-6 shows timing
characteristics.
Table 10-4. Pixel Characteristics for 2-Pixels-per-Clock Mode
Reg 2:0
Pixel Characteristics When Reg 30:6 is Cleared to ‘0’
Setting _{Total Number of Pixels}
Pixel Output
What the Pixels Represent
0 Total number is even. Output is on Channel ‘A’. Samples taken on half-rate ADCRCLK’s rising edge.
1 Total number is odd.
Output is on Channel ‘B’. Samples taken on half-rate ADCRCLK’s falling edge.
Table 10-5. Timing for 2-Pixels-per-Clock Mode
Time
Period
Timing Description
Tp, Td CLK Period, CLK Duty Cycle
t1 CLK Rise Time to ADCRCLK Rise Time
t2 ACDRCLK Period
t3 ACDRCLK Fall Time to ADCSYNC Rise Time
t4 Digital Data Transition
Min
Typ
Max Units
– See Table 10-3. –
ns
–
2.6
–
ns
–
t2 = 2 × Tp
–
ns
–
TBD
–
ns
3.8
5
TBD ns
Figure 10-6. AC Timing for 2-Pixels-per-Clock Mode
P+1
P+4
Analog Data In:
ARED
AGRN
ABLUE
CLK
ADCRCLK
ADCSYNC
P
Tp, Td
t3
P+3
P+2
t1
t2
‘A’ Channel Digital
Data Output
P-6
‘B’ Channel Digital
Data Output
P-5
ICS1531 Rev N 12/1/99
t4
P-4
P-2
P-3
P-1
Copyright © 1999, Integrated Circuit Systems, Inc.
All rights reserved.
68
P+5
P
P+1
December, 1999