ICS1531 Datasheet, PDF (67/76 Pages) Integrated Circuit Systems – Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator

ICS1531 Data Sheet - Preliminary
Chapter 10 Timing Diagrams
10.3 AC Timing Diagrams
10.3.1 Phase-Locked-Loop Timing for Digital Setup and Hold
The input HSYNC signal is used to generate the REF output signal. In the Phase/Frequency Detector, the
REF signal is compared with ADCSYNC (which provides the recovered HSYNC signal). Table 10-3 gives
the timing for these signals, and Figure 10-5 shows timing characteristics.
Table 10-3. Phase-Locked-Loop Timing
Time
Period
Timing Description
t1 Input HSYNC Rise Time to
REF Rise Time
Tp Clock Period
Min
Typ
TBD
7
Tp =
Input HSYNC Frequency
Result from:
Section 6.5.3, “Register 02h:
Fdbk Div 0 Register” and
Section 6.5.4, “Register 03h:
Fdbk Div 1 Register”
Max Units
TBD ns
ns
Td Clock Duty Cycle
t2 ADCSYNC Active Time
45-55
50-50
4 × Tp
55-45 %
ns
Figure 10-5. Timing for Phase-Locked Loop
HSYNC
t1
REF
Tp
Td
CLK
t2
ADCSYNC
ICS1531 Rev N 12/1/99
Copyright © 1999, Integrated Circuit Systems, Inc.
All rights reserved.
67
December, 1999